A non-volatile memory cell may be for example of the electrically erasable and programmable (EEPROM) type or else of the type with vertical selection transistor with a state transistor with floating gate selectable by way of the selection transistor connected in series with the state transistor.
With the increase in density in memory devices, floating-gate memory cells are getting ever closer together, this possibly generating interference between the charge stored in adjacent floating gates.
Hence, it is envisaged to use another type of non-volatile memory that may be referred to by the expression “memory cell of the type with charge trapping in a dielectric interface” better known by the person skilled in the art under the acronym “SONOS” or else “MONOS”, depending on the material used for the control gate.
More precisely, such a type of memory cell comprises a control gate separated from the substrate by a dielectric interface configured to trap charge.
Generally such an interface comprises a charge storage layer, for example made of silicon nitride (N), situated on a tunnel dielectric layer, for example formed of silicon dioxide (O), and under a dielectric blocking layer, for example also formed of silicon dioxide (O). The channel region of such a state transistor is for example formed in a silicon substrate (S). If the control gate is made of polysilicon (S), one then speaks of a SONOS device while if the control gate is at least partially metallic, one may speak of a device of the MONOS type.